
//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2012 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
// Version and Release Control Information:
//
// File Revision       : 127446
// File Date           :  2012-03-21 16:11:06 +0000 (Wed, 21 Mar 2012)
// Release Information : PL401-r0p1-00eac0
//------------------------------------------------------------------------------
//
//       *** AUTOMATICALLY GENERATED, DO NOT MODIFY ***
//
// --=========================================================================--


// AXI Interface
`define ID_WIDTH 4
`define ADDR_BUS_MAX 31
`define AWUSER_WIDTH 0
`define WUSER_WIDTH 0
`define BUSER_WIDTH 0
`define ARUSER_WIDTH 0
`define RUSER_WIDTH 0
`define AXVALID_WIDTH 1
`define DATA_WIDTH_SLAVE  64
`define DATA_WIDTH_MASTER 64

`define RS_REGD            0            // fully registered register slice
`define RS_FWD_REG         1            // registered on forward path only
`define RS_REV_REG         2            // registered on reverse path only
`define RS_STATIC_BYPASS   3            // register slice bypass




//------------------------------------------------------------------------------
// End of File
//------------------------------------------------------------------------------

